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The leading provider of system design, tools, software, IP and services, Cadence Design System’s Palladium Z1 Enterprise Emulation Platform has been adopted by Taiwan-based Global Unichip Corporation (GUC) to escalate system-on-chip (SOC) design and the semiconductor industry might be driven by innovation after this adoption. This adoption will aid GUC engineers to apply a more complex methodology for SOC verification tests, enhance complete debug visibility and accelerate verification by up to 795 times. The Cadence verification suit will provide engineers with high reliability and predictable turnaround times.
The Cadence verification suit will provide GUC engineers high reliability and predictable turnaround times for full-chip emulation model builds. The Palladium Z1 emulation platform will help GUC to improve system-on-silicon verification and optimized hardware and software integration at the early stage of the verification process. GUC engineers can debug quickly and explore design changes 20 times faster, which, other methodologies are not capable to do this.
GUC also adopted Cadence Xcelium Parallel Logic Simulation, JasperGold Formal Verification Platform and Verification IP (“VIP”) and is provided with automation, debug, tracking, management, and measurement of verification flows and engines, which will improve productivity and team accordance. The palladium Z1 emulation platform enables conformity with the adjacent suite engines and optimizes verification productivity and improves product quality.
“A high-performance ASIC verification solution is vital for driving our product innovations and business, and we need to continually strive to improve our overall product quality,” said Dr. Ken Chen, president at Global Unichip Corporation. “After comparing alternative solutions in the market, we selected Cadence’s Palladium Z1 Enterprise Emulation Platform for its effectiveness in ASIC verification productivity and use-model versatility. Adopting the Palladium Z1 emulation platform in conjunction with Xcelium Parallel Logic Simulation and the broader Cadence Verification Suite has enabled us to deliver flexible ASIC services that elevate our visionary IC customers to the next level of leadership in their respective markets.”
The Palladium Enterprise Emulation platform which is a part of the Cadence Verification Suite supports System Design Enablement strategy of the company, helps system and semiconductor companies to create complete, distinguished end products with more efficiency. The verification suit bears JasperGold, Xcelium, Palladium Z1 and Protium S1 core engines, fabric technologies, and solutions which improve design quality and production by satisfying verification requirements with extensive and various applications.