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By apacciooutlook | Thursday, February 04, 2016
TOKYO, JP: Renesas Electronics Corporation, a supplier of advanced semiconductor solutions, announces the development of hardware fault detection and prediction technologies for functional safety in automotive computing systems for the Autonomous-Driving Era, which is expected to arrive by the year 2020. The company has also developed an automotive computing system-on-chip (SoC), fabricated in 16 nm FinFET process supporting the ISO 26262 ASIL B standard for automotive functional safety.
Renesas has developed hardware fault detection technology based on a self-testing mechanism to resolve the issue of saving time while the SoC performs complex functions as it receives large amounts of data from cameras and sensors. Renesas’s technology makes it possible, even in the large-scale SoCs used in self-driving systems, to meet the criteria such as diagnostic coverage, which is expected to be required for the ISO 26262 ASIL B standard for functional safety.
In order to predict and suppress the momentary voltage droops caused by hardware faults Renesas has developed systems such as:
(1) Runtime self-test system that supports both time slicing and module independent tests: the challenge of saving time in the SoC while it performs self-tests, Renesas implemented built-in-self-tests (BIST) systems in the CPU and GPU function blocks, and an integrated controller for these BIST systems. Renesas developed functions that enable these runtime self-tests to be executed with test time slicings (a) By executing the runtime self-test on one specific CPU in the CPU cluster, which consists of four CPUs, and continuing program execution on the remaining three CPUs, and (b) dividing the GPU self-test into multiple sections and executing those sections in a time-sliced manner.
2) In order to suppress hardware faults due to voltage droop, Renesas has developed the following three systems:
Ultrafast voltage sampling system: Renesas developed a high-speed voltage sampling system which adjusts the voltage difference with time.
Voltage droop prediction system: This system predicts the voltage droop four cycles in advance based on the voltage information acquired from the voltage sampling system.
High-functionality clock control system: This system combines a clock gating circuit and a clock divider circuit and immediately stops the clock supply after receiving the clock stop request to suppress voltage droop. By using the above three systems, the voltage droops that occur are prevented in advance, from causing any hardware faults to the SoC, Reneas has designed large scale SoCs to the ISO 26262 standard.